This invention relates to a transistor circuit and in particular to a transistor circuit using a vertical NPN transistor.
In an integrated circuit device in which a desired transistor circuit is constituted by a combination of an NPN transistor and PNP transistor, the NPN transistor is of a vertical transistor and PNP transistor is of a lateral transistor. By controlling the depth of diffusion the base of the NPN transistor can be designed to have a very narrow width of about 0.8 to 1.5 .mu.m, a distance between the emitter and the collector of the NPN transistor. As a result, the cutoff frequency of the vertical NPN transistor has a high value of 200 to 300 MHz and the percentage in which carriers injected into the base are injected into the collector becomes great, representing a current amplification factor hFE of about 100. The base width of the lateral PNP transistor has a great value of about 10 .mu.m, for it is restricted by the precision with which a mask is effected in the manufacture of an integrated circuit. For this reason, the cutoff frequency of the lateral PNP transistor has a low value of several MHz and the percentage in which carriers injected into the base is injected into the collector becomes small, representing a current amplification factor hFE of about 1 to 10. In this way the lateral PNP transistor is very inferior in performance to the vertical NPN transistor and, where an integrated circuit is designed using the PNP transistor, the drawbacks of the lateral PNP transistor present a bar to the realization of a high performance IC device.